With the rapid development of computer system technology, there is the continuous technological advancement of hardware equipment with high computing performance. Currently, cluster system is widely applicable to high performance computing field increasingly. The cluster system is a unit system which integrates a plurality of independent servers in the network domain and is managed based on unity mode to provide reliable services for client's workstation. The operating system and application program file of each server are stored in the local storage. When one server in one node malfunctions, another server in another node takes over all the application programs executed in the one server. If an application program service in the one server causes failure, the application program service is re-started or taken over by another server. Therefore, it is very important to synchronize the memory data of the servers.
Referring to FIG. 1, it is a schematic view of a conventional “2U” or “4U” cluster system. The memory data of two motherboards are synchronized by redundant motherboards therebetween while employing a conventional network interface card (NIC) and software. For the purpose of higher transmission bandwidth and rapid response time, most of the cluster systems adopt the NIC, i.e. network adapter, with 10G to implement the data synchronization wherein the bandwidth reaches 20G per second. As shown in FIG. 1, the first motherboard 11 includes a first NIC 112 with 10G and the second motherboard 13 includes a second NIC 132 with 10G. The first NIC 112 is connected to the second NIC 132 by way of the network cables. The central processing units (CPUs) and NICs in each motherboard are compatible to Peripheral Component Interconnect Express (hereinafter PCIE). While synchronizing the memory data, it is required to transmit the PCIE packet data of first CPU 111 in one, e.g. the first motherboard 111, of motherboards to the first NIC 112. The first NIC 112 converts the PCIE packet data to network packet data to be synchronized with the second NIC 132 of the second motherboard 13. In other words, the PCIE packet data is regarded as general PCIE data and the general PCIE data are re-packaged to form network packets according to network packet protocol wherein the network packets occupy a lot of bits. The second NIC 132 of the second motherboard 13 converts the network packets into PCIE packet data to be sent to the second CPU 131 of the second motherboard 13. The drawbacks of the aforementioned system are the NIC with 10G additionally disposed in each motherboard and the packet conversion, which wastes approximately 20% of data transmission bandwidth.